Thin-film transistor (TFT) misalignment and parasitic capacitance can degrade the quality and performance of electronic devices such as liquid crystal displays (LCDs). One known attempt to correct for TFT misalignments and any associated increase in parasitic capacitance is found in U.S. Pat. No. 5,191,451 to Katayama et al (“the '451 patent”). FIG. 1 depicts the “double TFT” arrangement 100 of the '451 patent. Source line 104 connects to the TFT via source electrode 106. Two gate electrodes 108 are connected to gate line 102. Two drain electrodes 110 connect to the pixel and are formed such that the two gate electrodes 108 affect conduction from the source electrode to the drain electrodes when activated. It is noted that there are two crossover regions 112 that are connected to TFT may produce additional parasitic capacitance between the gate and the source. As discussed in the '451 patent, any vertical misalignment of the TFT placement is somewhat corrected by this double TFT arrangement as is discussed therein.
Another manner of reducing the ill effects of TFT misalignment is shown in U.S. Pat. No. 5,097,297 to Nakazawa (“the '297 patent”). FIG. 4 depicts a TFT 400 made in the manner taught in the '297 patent. As may be seen in FIG. 2, gate line 402 delivers the gate signal to gate electrode 408. Source line 404 sends image data to source electrodes 406. When the gate electrode is activated, the image data is transferred to the pixel via the drain electrode 410. It is noted that this TFT embodiment contains only one gate crossover 412 which aids in reducing parasitic capacitance.
Furthermore, prior LCDs use the same orientation to align transistor in the pixel area of the display. However, for alternative pixel arrangements, transistors may need to be located in unconventional locations of a pixel area, while addressing misalignment and parasitic capacitance.